The present invention relates to a technology which is effective when applied to a device structure and a device manufacturing technique in a semiconductor device (or semiconductor integrated circuit device) such as a vertical planar power MOSFET or a trench-gate MOSFET and a method of manufacturing the semiconductor device.
Japanese Unexamined Patent Publication No. 2007-173783 (Patent Document 1) or U.S. Pat. No. 7,928,470 (Patent Document 2) corresponding thereto discloses a technique in which, in a silicon-based vertical planar power MOSFET, a P−-type body region (channel region) is formed over the entire surface of a super junction drift area by epitaxial growth.
Also, Japanese Unexamined Patent Publication No. 2008-283151 (Patent Document 3) or US Patent Publication No. 2011-136308 (Patent Document 4) corresponding thereto discloses a technique in which, in a silicon-based trench power MOSFET, a P-type body region (channel region) is formed over the entire surface of a super-junction drift area by epitaxial growth.